Semiconductor device and manufacturing method thereof

ABSTRACT

The object of the present invention is to provide a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor, which has a high degree of reliability and excellent drain current characteristics. The gist of the invention for attaining the object resides in disposing a silicon nitride film to the side wall of a trench for an active region in which the n-type channel field effect transistor is formed and disposing the silicon nitride film only in the direction perpendicular to the channel direction to the sidewall of the trench for the active region of the p-type channel field effect transistor. According to the present invention, a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor of excellent current characteristics can be provided.

TECHNICAL FIELD

The present invention relates to semiconductor devices and, more inparticular, it relates to a semiconductor device having an n-typechannel field effect transistor and a p-type channel field effecttransistor.

BACKGROUND ART

In recent years, the processing performance required for semiconductordevices such as LSI has become severer along with the progress ofinformation communication equipment and it has been attempted toincrease the operation speed of transistors. In particular,complementary field effect transistors comprising an n-type channelfield effect transistor and a p-type channel field effect transistorhave been used generally since they consume less electric power. Itsoperation speed has been increased mainly by the refinement of thestructure being supported by the progress of lithography for fabricatingsemiconductor devices. However, the required minimum fabrication size(minimum fabrication size for gate) is reduced to less than the level ofthe wavelength of light used for the lithography to bring about adifficulty in further refinement of fabrication.

In view of the above, as a means for increasing the operation speed ofthe n-type channel field effect transistor, a method of inducing strainsto silicon in the channel portion of the field effect transistor hasbeen proposed. It has been known so far that the electron mobility(effective mass) changes when silicon crystals are strained. JapanesePatent Laid-open No. 11-340337 discloses a method of usingsilicon-germanium of lager lattice constant than that of silicon for theunderlying film forming the field effect transistor, and epitaxiallygrowing a silicon layer thereover thereby providing silicon to be achannel portion with strains to enhance the mobility and increase theoperation speed of the transistor.

However, when materials of different lattice constants of crystals areepitaxially grown under lattice matching as described above, the strainenergy caused in the crystals increases to bring about a problem ofincluding dislocation in the crystals at a film thickness greater than acertain critical thickness. Further, adoption of an additionalproduction apparatus caused by the introduction of unusual material ofsilicon-germanium increases the cost in the production process ofsemiconductor devices such as LSI. Thus, the method described above hasnot yet been put to practical use.

Further, while the complementary field effect transistor comprises ann-type channel field effect transistor using electrons as carriers andan n-type channel field effect transistor using holes as carries, it ispreferred to increase the operation speed for each of the n-type channeland p-type channel transistors in order to increase the operation speedof the semiconductor device.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a semiconductor devicehaving an n-type channel field effect transistor and a p-type channelfield effect transistor, which is excellent in the drain currentcharacteristics.

The present invention for solving the subject described above is to bedescribed.

(1) A semiconductor device is characterized by comprising: a fieldregion in which an insulative film is buried to the inside of a trenchformed to the main surface of a semiconductor substrate; and a pluralityof active regions adjacent to the field region, the active regionshaving a first active region formed with an n-type field effecttransistor and a second active region formed with a p-type field effecttransistor; wherein: an oxidation preventive film for suppressingoxidation of the semiconductor substrate in the trench is disposed on alateral surface of the trench in the field region adjacent to the firstactive region on a side of the first active region which is located in adirection of connecting a source and a drain of the n-type field effecttransistor; and the oxidation preventive film is not disposed on thelateral surface of the trench in the field region adjacent to the secondactive region which is located in a direction of connecting a source anda drain of the p-type field effect transistor.

The insulative layer can use a material having lower conductivity thanthat of the silicon substrate or the like located on the peripherythereof, for example, a silicon oxide layer. Further, the insulator isdeposited over the oxidation preventive film. The direction ofconnecting the source and the drain can be, for example, the so-calledchannel direction. In this case, preferably, the stress exerted on thelongitudinal direction of the gate electrode is a lower compressionstress than the compression stress exerted in the source and draindirection of the gate electrode, or the stress exerted in thelongitudinal direction of the gate electrode is a tensile stress and thestress exerted in the source-drain direction of the gate electrode is acompression stress.

(2) The semiconductor device described above is characterized in thatthe oxidation preventive film is a nitride film.

A silicon nitride film can be provided, for example, as the oxidationpreventive film for preventing the substrate in the trench fromoxidation, on the sidewall of the trench of the field region adjacentwith the first active region having the p-type field effect transistor.

(3) The semiconductor device as described above is characterized in thatthe oxidation preventive film for suppressing the oxidation of thesemiconductor substrate in the trench is disposed on the lateral surfaceof the trench in the field region adjacent to the second active regionwhich is located in the longitudinal direction of the gate electrodesituated between the source and the drain of the n-type field effecttransistor.

The longitudinal direction of the gate electrode can be a directionperpendicular to (e.g., at a right angle to) the channel direction.

(4) The semiconductor device as described above is characterized in thatthe oxidation preventive film for suppressing the oxidation of thesemiconductor substrate in the trench is disposed on the lateral surfaceof the trench in the field region adjacent to the second active regionwhich is located in the longitudinal direction of the gate electrodelocated between the source and the drain of the p-type field effecttransistor.

(5) A semiconductor device is characterized by comprising: a fieldregion in which an insulative film is buried in the inside of a trenchformed in a main surface of a semiconductor substrate; a first activeregion formed with an n-type field effect transistor; and a secondactive region formed with a p-type field effect transistor; wherein: anoxidation preventive film for suppressing oxidation of the semiconductorsubstrate in the trench is disposed on a lateral surface of the trenchin the field region adjacent to the first active region on a side of thefirst active region which is located in a direction of connecting asource and a drain and in a direction perpendicular to the direction ofconnecting the source and drain of the n-type field effect transistor;and the oxidation preventive film is not disposed on the lateral surfaceof the trench in the field region adjacent with the second active regionon a side of the second active region which is located in the directionof connecting a source and a drain of the p-type field effecttransistor, and the oxidation preventive film for suppressing theoxidation of the semiconductor substrate in the trench is disposed onthe lateral surface of the trench which is located in the directionperpendicular the direction of connecting the source and the drain.

(6) A semiconductor device is characterized by comprising: a fieldregion in which an insulative film is buried in the inside of a trenchformed in a main surface of a semiconductor substrate; and a pluralityof active regions adjacent to the field region, the active region havinga first active region formed with an n-type field effect transistor anda second active region formed with a p-type field effect transistor;wherein: an oxidation preventive film for suppressing oxidation of thesemiconductor substrate in the trench is disposed on a lateral surfaceof the trench in the field region adjacent to the first active region ona side of the first active region which is located in a direction ofconnecting a source and a drain of the n-type field effect transistor;the active region having a third active region adjacent to the secondactive region by way of a field region and a fourth active regionadjacent to the second active region from a side opposite to the side ofthe first active region; the third active region and the fourth activeregion are located in the direction of connecting the source and thedrain of the p-type field effect transistor formed in the second activeregion; and a field region located between the second active region andthe third active region and a field region located between the secondactive region and the fourth active region has an area of the same widthwithin a range of fabrication dimensional error.

Further, “within a range of fabrication dimensional error”, in otherwords, within the range of variations means that it is within the rangeof variations in usual fabrication, preferably, that the size may beidentical at 0.05 μm or less. It is more desirable to be within therange of the fabrication scattering for the gate length Lg of the gateelectrode in other circuit, for example, a memory cell or 2 NAND circuitin the semiconductor substrate to which the semiconductor device of thisembodiment is formed. It is further preferably 0.05 μm or less and,further preferably, 0.03 μm or less.

(7) The semiconductor device described above is characterized in thatthe n-type field effect transistor and the p-type field effecttransistor constitute a sense amplifier circuit.

(8) The semiconductor device described above is characterized in thatthe n-type field effect transistor and the p-type field effecttransistor constitute a differential amplification circuit.

(9) The semiconductor device described above is characterized in thatthe n-type field effect transistor and the p-type field effecttransistor constitute a NAND circuit.

(10) The semiconductor device described above characterized in that anoxide film is formed between the oxidation preventive film and thesemiconductor substrate formed with the trench.

(11) A method of manufacturing a semiconductor device having an n-typefield effect transistor and a p-type field effect transistor comprisingthe steps of: forming a pad oxide film on a semiconductor substrate;forming a nitride film on the pad oxide film; removing the pad oxidefilm and the nitride film in a region forming a field region adjacent toan active region thereby forming an opening; forming a trench on thesemiconductor substrate in the opening; forming an oxidation preventivefilm for preventing oxidation of the semiconductor substrate in thetrench on the lateral surface of the trench of the field region adjacentwith the first active region surrounded with the trench, and depositingan insulative film over the oxidation preventive film thereby buryingthe trench; depositing the insulative film to bury the trench withoutdisposing the oxidation preventive film to the lateral surface of thefield region adjacent with the second active region surrounded with thetrench; removing the pad oxide film and the nitride film in the firstand the second active regions; and forming an n-type field effecttransistor in the first active region, and forming a p-type field effecttransistor in the second active region, in which the lateral surface ofthe trench not disposed with the oxidation preventive film is disposedso as to be situated in the direction of connecting the source and thedrain of the p-type field effect transistor.

(12) The method of manufacturing a semiconductor device described aboveis characterized by further including the steps of forming an oxidationpreventive film on the lateral of the trench of the field regionadjacent with the first active region and to the lateral surface of thetrench in the field region adjacent with the second active region; andremoving the oxidation preventive film on the lateral surface of thetrench in the field region adjacent to the second active region.

The present inventors have measured the stress dependency of the draincurrent in the field effect transistor and found that the stressdependency is different between the n-type channel field effecttransistor and the p-type channel field effect transistor. FIG. 4 showsthe experimental results of the stress dependency of the drain currentin the n-type channel field effect transistor and the p-type channelfield effect transistor. A stress loading experiment is performed ontransistors formed on the Si (001) face such that the drain currentflows parallel with the <110> axis. The gate electrode of the evaluatedfield effect transistors is 0.2 μm. Further, the stress with respect tothe direction includes an in-channel plane axis stress parallel with thedrain current (hereinafter referred to as channel-parallel-stress) andan in-channel plane axis stress orthogonal to the drain current(hereinafter referred to as channel-orthogonal-stress) flowing throughthe channel of the field effect transistor. A positive stress signrepresents tensile stress and negative stress sign represents acompression stress. It has been demonstrated that for the n-type channelfield effect transistor, the drain current increases relative to thetensile stress (at about 4%/100 MPa under the stress parallel with thechannel and at about 2%100 MPa under the stress orthogonal to thechannel). On the other hand, for the p-type channel field effecttransistor, the drain current increases in the direction orthogonal tothe channel (at about 4%/100 MPa) but the drain current decreases in thedirection parallel with the channel (at about 7%/100 MPa).

The stress and the strain are in a relation proportional to each otherso long as it is concerned with the region of elastic deformation. Theexperimental results described above shows that the drain current isincreased when tensile stress is applied parallel with the channel tothe n-type channel field effect transistor. This is probably because thecrystal lattice of silicon constituting the channel is strained in thetensile direction parallel with and in the channel plane compared withthat before loading stress, increasing the mobility of electrons. Thatis, the present inventors have demonstrated that the drain currentcharacteristics of the n-type channel and the p-type channel fieldeffect transistor depend on the direction of the strain caused in thecrystal lattice of silicon constituting the channel and the absolutevalue thereof.

The effect of the stress generated in the field effect transistor on thetransistor characteristics has been studied by focusing on, for example,the stress dependency of the mutual conductance (Gm) as one of thecharacteristics of the field effect transistor (Akemi Hamada, et al.,IEEE trans. Electron Devices, vol. 38, No. 4, pp. 895–900, 1991).However, fluctuation of the characteristics of the field effecttransistor due to the stress has not been attached much importance. Thisis probably because the sensitivity of the transistor itself to thestress is low. FIG. 5 comparatively shows the experimental results ofthe stress dependence of Gm (gate length: 2 μm) in the above-mentionedliterature (Akemi Hamada, et al., IEEE trans. Electron Devices, vol. 38,No. 4, pp. 895–900, 1991) and the experimental results of the stressdependency of Gm performed by the present inventors (gate length: 0.2μm) . The comparison was made for the load stress in the directionparallel with the channel for the n-type channel field effecttransistors. The transistor of the generation where a gate length is 0.2μm is about four times the transistor in the generation where the gatelength was 2 μm in the dependence of Gm on the stress. That is, thisshows that the sensitivity of the transistor characteristics to thestress increases along with the progress of the transistor generation.

According to the invention, in the semiconductor device having an n-typechannel field effect transistor and the p-type channel field effecttransistor, the n-type channel and the p-type channel field effecttransistors are fabricated in a different manner in their structuressuch that the compression stress generated in the channel portion of then-type channel is decreased or transformed to the tensile stress, andthe state of stress in the direction orthogonal to the channel directionis transformed to the stress in the tensile direction compared with theparallel direction in the p-type channel transistor, or such that theentire portion is in the state of the compression stress.

Since the drain current characteristics can be improved both for then-type channel and the p-type channel transistors, a semiconductordevice excellent in the performance as a whole can be provided.

Further, since silicon-germanium is not used in the semiconductordevice, the high reliable semiconductor device with suppresseddislocation or the like can be provided.

According to the invention, a semiconductor device having an n-typechannel field effect transistor and a p-type channel field effecttransistor, which is excellent in drain current characteristic, can beprovided. Further, a semiconductor device having an n-type channel and ap-type channel transistor that are excellent in drain characteristic canbe provided.

In particular, the invention is preferably applied to a semiconductordevice having a complementary type field effect transistor comprising ann-type channel field effect transistor and a p-type channel field effecttransistor.

DESCRIPTION OF THE ACCOMPANYING DRAWINGS

FIG. 1 shows an inverter circuit of a first embodiment according to thepresent invention;

FIG. 2 shows a layout of the inverter circuit according to the firstembodiment of the invention;

FIG. 3 shows a cross-sectional view of the inverter circuit layoutaccording to the first embodiment of the invention;

FIG. 4 is a graph showing the experimental results of the stressdependency of the drain current in n-type channel and p-type channelfield effect transistors;

FIG. 5 is a graph showing the experimental results of the difference ofthe dependency of the mutual conductance (Gm) on the stress depending onthe generations of the field effect transistor;

FIG. 6 is a conceptional diagram explaining the generation of stress inan STI structure;

FIG. 7 is a graph showing the analysis of the dependence of theoxidation-induced stress on the STI width;

FIGS. 8A to 8H are cross-sectional views showing a method of depositinga silicon nitride film inside the STI trench;

FIG. 9 shows another layout of the inverter circuit according to thefirst embodiment of the invention;

FIG. 10 shows a 2-input NAND circuit;

FIG. 11 is a layout in a case of applying the invention to the 2-inputNAND circuit;

FIG. 12 shows a sense amplifier circuit;

FIG. 13 is a layout in a case of applying the invention to the senseamplifier circuit;

FIG. 14 shows a layout of an inverter circuit according to a secondembodiment of the invention;

FIG. 15 shows a layout of an 2-input NAND circuit according to a secondembodiment of the invention; and

FIG. 16 shows a layout of the sense amplifier circuit according to thesecond embodiment of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Preferred embodiments of the present invention are to be describedbelow. The invention is not restricted to the following embodiments butis applicable to other embodiments.

The invention is to be described by way of the first embodiment withreference to FIG. 1. FIG. 1 is an inverter circuit diagram of thisembodiment; FIG. 2 is a layout of the inverter circuit; and FIG. 3 is across-sectional view taken along line A–A′ of FIG. 2.

As shown in FIG. 2, this embodiment comprises a p-type channel fieldeffect transistor Q1, an n-type channel field effect transistor Q2 andinterconnections for connecting the transistors electrically.

The n-type channel field effect transistor Q2 formed on a substrate(sub1) 1 comprises an n-type source (soce 1) 6, a drain (drain 1) 7, agate electrode (poly-Si) 9 and a gate oxide film (gato-ox) 8 formed on ap-type well layer (pwell) 4. Further, the p-type channel field effecttransistor Q1 comprises a p-type source (soce) 6, a drain (drain) 7, agate electrode (poly-Si) 9 and a gate oxide film (gato-ox) 8 in the samemanner as that for the n-channel formed in an n-type well layer (nwell)5. Further, to connect the transistors for constituting a circuit,contacts (contact) 10 and interconnections (AL) 18 are disposed.Further, double head arrows are shown to denote the longitudinaldirection of the gate electrode and the direction of source-drain(channel direction) crossing (perpendicular to) the direction of thegate electrode in FIG. 2.

Further, as shown in FIG. 3, a shallow trench isolation (STI) formed byfilling a trench with a thick oxide film (SiO₂B) 15 surrounds theperiphery of each of transistors Q1 and Q2 for electrically isolatingthem (the region in which the field effect transistor is formed ishereinafter referred to as an active region “active”). A silicon nitridefilm (SiNA) 16 is deposited on the trench sidewall in STI adjacent tothe n-type channel field effect transistor Q2 not only in the channeldirection but also in the direction perpendicular to the channeldirection. Here, the channel direction is a direction connecting thesource 6 and drain 7, that is, a direction perpendicular to thelongitudinal direction of the gate electrode between the source 6 anddrain 7. In addition, the direction crossing the channel direction is alongitudinal direction of the gate electrode situated between the source6 and drain 7. On the other hand, a silicon nitride film (SiNA) 16 isformed on the trench sidewall of the p-type channel field effecttransistor Q1 only in the direction perpendicular to the channeldirection. Then, the silicon oxide film (SiO₂B) fills the trenchthereover for isolation. The silicon nitride film (SiN) is not disposedon the trench sidewall situating in the channel direction.

The function and the effect of the semiconductor device according tothis embodiment is to be described. In the development of semiconductordevices such as LSIs, an improvement in the drain current in the fieldeffect transistor (an increase in the drain current) has proceeded yearby year. The present inventors have demonstrated that the drain currentchanges depending on the stress given to the transistor and have found amethod of improving the drain current in both of an n-type channel and ap-type channel transistor of a complementary field effect transistorhaving the p-type channel field effect and the n-type channel fieldeffect transistor.

FIG. 4 shows the stress dependency of the drain current in the fieldeffect transistor. The figure demonstrates that the drain currentincreases in the n-type channel field effect transistor by the tensilestress, whereas the drain current increases in the p-type channel fieldeffect transistor by the compression stress.

As shown in FIG. 6, STI has a structure of engraving a trench in asilicon substrate and burying a silicon oxide film (SiO₂B) 15 inside thetrench and, as shown in FIG. 3, STI is formed adjacent to thetransistor. Usually, the transistor is formed after the formation ofSTI. A number of oxidation steps including the step for the gate oxidefilm are present in the formation of the transistor. In the oxidationstep, since oxygen as oxidizing species diffuses in the oxide film(SiO₂B) 15 inside the trench of STI, the oxide film SiO₂C is grown alsoon the trench sidewall. Upon transformation of a film from silicon tosilicon oxide, the film causes approximately twice volume expansion.Since the volume expansion is constrained by the buried oxide film, acompression stress field is formed as a reaction thereof in atransistor-forming region as shown by hatched lines in FIG. 6. When suchcompression stress field is formed in the region forming the n-typechannel field effect transistor, drain current lowers as shown in FIG.4. FIG. 7 shows an example of analyzing the state of the compressionstress by use of an oxidation simulator in which the compression stressvalue increases as the STI width decreases. This is because thecompression stresses generated in the trench sidewall (both sides)increases by the interference in the trench due to the decreased STIwidth. That is, this means that electrical characteristics of thetransistors Q1 and Q2 change depending on the width of STI around thetransistors Q1 and Q2. While it is probable that the problem can beovercome by the layout for all the circuits with a constant STI width,it is not practical because of various restrictions on the layout. Inview of the above, in the invention, occurrence of the compressionstress can be suppressed by depositing a silicon nitride film as a maskfor oxidation on the lateral surface of the trench for preventing thesubstrate on the trench side wall from oxidation in order not to oxidizethe trench side wall even when the oxidation species are diffused in theSTI region.

The drain current in the p-type channel field effect transistor can beincreased by applying a stress in the compression direction parallel tothe channel while applying a stress in the tensile directionperpendicular to the channel in view of FIG. 4. Then, in order to obtainsuch a stress field, the silicon nitride film is deposited to the STItrench sidewall only in the direction parallel to the channel.

Further, in the n-type channel field effect transistor, since the draincurrent decreases by the compression stress irrespective of thedirection of the stress parallel or perpendicular to the channel, thesilicon nitride film is deposited on the sidewall of the STI trenchsurrounding the n-type channel field effect transistor.

Accordingly, in the semiconductor device having the n-type channel fieldeffect transistor and the p-type channel field effect transistor, thestress caused by the STI structure (STI stress) shown above iscontrolled depending on the p-type channel field effect transistor andthe n-type channel field effect transistor, so that the improvement inthe drain current both for the n-type channel and the p-type channeltransistor can be promised. Consequently, the performance of the entirecircuit can be enhanced.

FIG. 3 is a cross-sectional view taken along line A–A′ of FIG. 2. Thewell regions 4 (pwell) and 5 (pwell) are formed on the silicon substrate(sub) 1 and STI is formed for trench isolation at the boundary for eachof the well regions. Further, the silicon nitride (SiNA) 16 is formed asan oxidation preventive mask inside the trench of STI surrounding then-type channel field effect transistor Q2. Then, trench isolation SiO₂B15 can be deposited thereover. The n-type channel field effecttransistor Q2 comprises a source (soce 1) 6, a drain (drain 1) 7, and agate electrode (gato-ox) 9. In addition, a p-type channel field effecttransistor Q1 comprises a source (soce) 6, a drain (drain) 7, and a gateelectrode (gato-ox) 9. They are connected by way of contacts 10 tointerconnections (AL) 18 to constitute an inverter circuit.

The method of depositing the silicon nitride film in the STI structurecan be performed by the method as shown in FIG. 8. The formation methodis to be described.

(1) A pad oxide film (SiO₂) 12 is formed on the silicon substrate (sub)12. A first silicon nitride film (SiN) 13 is formed the pad oxide film12. The first silicon nitride film (SiN) 13 and the pad oxide film(SiO₂) 12 are removed at desired positions to expose the surface of thesilicon substrate (sub) 1. Subsequently, a predetermined trench isformed using the first silicon nitride film (SiN) 13 as a mask (FIG.8A).

(2) The surface of the silicon substrate (sub) 1 in the trench isoxidized to form an oxide film (SiO₂A) 14 (FIG. 8B).

(3) A second silicon nitride film (SiNA) 16 is formed on the exposedsurface (FIG. 8C).

(4) A resist film (resist) 17 is coated over the entire substrate, andits desired portion is removed by exposure to light (FIG. 8D).

(5) A portion of the second silicon nitride film (SiNA) 16 is removed byisotropic dry etching using the resist film (resist) 17 as a mask (FIG.8E) (an active side trench wall opposite to the active region formedwith the n-type field effect transistor).

(6) The resist film (resist) 17 is removed and the oxide film (SiO₂B) 15is buried inside the trench (FIG. 8F).

(7) The oxide film (SiO₂B) 15 formed over the first silicon nitride film(SiN) 13 is removed for planarization (FIG. 8G).

(8) The first silicon nitride film (SiN) 13, and the pad oxide film(SiO₂) 12 are removed (FIG. 8H).

According to the method described above, the silicon nitride film can beinwardly deposited on the sidewall only on one side of the STI trench.

(9) Then, a device comprising the gate oxide film 8 and the gateelectrode 9, and interconnections also shown in FIG. 3 are formed overthe exposed silicon substrate 1.

The layout for the inverter circuit in FIG. 2 can be modified to that asshown in FIG. 9. Further, when the invention is applied to a 2-inputNAND shown in FIG. 10, its layout is as shown in FIG. 11.

Further, two transistors (Q7 and Q8) in the sense amplifier circuit ofFIG. 12 should be identical in characteristics. In such a case, itslayout is as shown in FIG. 13. In this case, STI stress in the directionparallel with the channel of the transistors Q7 and Q8 are preferablyidentical between the two transistors. Therefore, it is preferred todispose active regions by way of STI so as to be adjacent to thetransistors Q7 and Q8. It is effective that the STI stress exerted onthe transistors Q7 and Q8 is high compression stress in view of FIG. 4in order to improve the drain current. For this end, it is preferredthat STI is fabricated to have a minimum width S1 during the LSI formingprocess. The minimum width Si is less than the distance between theactive region having the transistors Q7 and Q8 and the correspondingactive region having transistors Q9 and Q10. It can be, for example,formed to 0.25 μm or less.

As shown in FIG. 4, in the p-type channel field effect transistor, tomaximize the drain current, it is effective to change the direction ofstress remaining in the directions parallel and perpendicular to thechannel. However, a change in the drain current due to the stress isgreater in the case of applying the stress in parallel with the channel(about 4%/100 MPa) than in the case of applying the stress crossing tothe channel (about 2%/100 MPa). Accordingly, the drain current can beincreased (4−2=2%) in total, by applying the compression stress to theregion for forming the p-type channel field effect transistor(irrespective of the channel direction). Accordingly, the improvement inthe drain current for both the n-type channel and p-type channeltransistors can also be promised by forming the silicon nitride film onthe trench side wall only for STI adjacent to the n-type channel fieldeffect transistor so as to surround the transistor as shown in thedrawing. Characteristics as the entire circuit can be improved.

The layout of applying the method described above to the invertercircuit in FIG. 1, the 2-input NAND circuit in FIG. 10 and the senseamplifier circuit in FIG. 12 are as shown in FIGS. 14, 15, and 16,respectively.

For easy understanding of the drawings, principal references are to beexplained below.

Silicon substrate-1, shallow trench isolation-2, transistor formingregion (active)-3, p-type well-4, n-type well-5, source (soce, soce1)-6, drain (drain, drain 1)-7, gate oxide film-8, gate electrode-9,contact-10, interlayer insulative film (TEOS)-11, pad oxide film-12,first silicon nitride film-13, oxide film-14, buried oxide film-15,second silicon nitride film-16, resist-17, interconnection-18, Q1, Q3,Q4, Q7, Q8-p-type channel field effect transistor, Q2, Q5, Q6, Q9,Q10-n-type channel field effect transistor

INDUSTRIAL APPLICABILITY

According to the present invention, a semiconductor device having ann-type channel field effect transistor and a p-type channel field effecttransistor excellent in current characteristics can be provided.

1. A semiconductor device comprising: a field region in which aninsulative film is buried to the inside of a trench formed to the mainsurface of a semiconductor substrate; and a plurality of active regionsadjacent to the field region, the active regions having a first activeregion formed with an n-type field effect transistor and a second activeregion formed with a p-type field effect transistor; wherein: anoxidation preventive film for suppressing oxidation of the semiconductorsubstrate in the trench is disposed on a lateral surface of the trenchin the field region adjacent to the first active region on a side of thefirst active region which is located in a direction of connecting asource and a drain of the n-type field effect transistor; the oxidationpreventive film is not disposed on the lateral surface of the trench inthe field region adjacent to the second active region which is locatedin a direction of connecting a source and a drain of the p-type fieldeffect transistor and the oxidation preventive film for suppressing theoxidation of the semiconductor substrate in the trench is disposed onthe lateral surface of the trench in the field region adjacent to thesecond active region which is located in a longitudinal direction of agate electrode located between the source and the drain of the p-typefield effect transistor.
 2. The semiconductor device according to claim1, wherein the oxidation preventive film is a nitride film.
 3. Thesemiconductor device according to claim 1, wherein the oxidationpreventive film for suppressing the oxidation of the semiconductorsubstrate in the trench is disposed on the lateral surface of the trenchin the field region adjacent to the second active region which islocated in the longitudinal direction of a gate electrode locatedbetween the source and the drain of the n-type field effect transistor.4. A semiconductor device according to claim 1, wherein the n-type fieldeffect transistor and the p-type field effect transistor constitute asense amplifier circuit.
 5. A semiconductor device according to claim 1,wherein the n-type field effect transistor and the p-type field effecttransistor constitute a differential amplification circuit.
 6. Asemiconductor device according to claim 1, wherein the n-type fieldeffect transistor and the p-type field effect transistor constitute aNAND circuit.
 7. A semiconductor device according to claim 1, wherein anoxide film is formed between the oxidation preventive film and thesemiconductor substrate formed with the trench.
 8. A semiconductordevice comprising: a field region in which an insulative film is buriedin the inside of a trench formed in a main surface of a semiconductorsubstrate; a first active region formed with an n-type field effecttransistor; and a second active region formed with a p-type field effecttransistor; wherein: an oxidation preventive film for suppressingoxidation of the semiconductor substrate in the trench is disposed on alateral surface of the trench in the field region adjacent to the firstactive region on a side of the first active region which is located in adirection of connecting a source and a drain and in a directionperpendicular to the direction of connecting the source and drain of then-type field effect transistor; and the oxidation preventive film is notdisposed on the lateral surface of the trench in the field regionadjacent with the second active region on a side of the second activeregion which is located in the direction of connecting a source and adrain of the p-type field effect transistor, and the oxidationpreventive film for suppressing the oxidation of the semiconductorsubstrate in the trench is disposed on the lateral surface of the trenchwhich is located in the direction perpendicular the direction ofconnecting the source and the drain.
 9. A semiconductor devicecomprising: a field region in which an insulative film is buried in theinside of a trench formed in a main surface of a semiconductorsubstrate; and a plurality of active regions adjacent to the fieldregion, the active region having a first active region formed with ann-type field effect transistor and a second active region formed with ap-type field effect transistor; wherein: an oxidation preventive filmfor suppressing oxidation of the semiconductor substrate in the trenchdisposed on a lateral surface of the trench in the field region adjacentto the first active region on a side of the first active region which islocated in a directio of connecting a source and a drain of the n-typefield effect transistor; the active region having a third active regionadjacent to the second active region by way of a field region and afourth active region adjacent to the second active region from a sideopposite to the side of the first active region; the third active regionand the fourth active region are located in the direction of connectinthe source and the drain of the p-type field effect transistor formed inthe second active region; and a field region located between the secondactive region and the third active region and a field region locatedbetween the second active region and the fourth active region has anarea of the same width within a range of fabrication dimensional error.10. A method of manufacturing a semiconductor devices, including ann-type field effect transistor and a p-type field effect transistors,comprising the steps of: forming a pad oxide film on a semiconductorsubstrate; forming a nitride film on the pad oxide film; removing thepad oxide film and the nitride film in a region fanning a field regionadjacent to an active region thereby forming an opening; forming atrench in the semiconductor substrate in the opening; forming anoxidation preventive film for preventing oxidation of the semiconductorsubstrate in the trench on a lateral surface of the trench of the fieldregion adjacent to the first active region surrounded with the trench,and depositing an insulative film on the oxidation preventive filmthereby burying the trench; depositing the insulative film therebyburying the trench with the oxidation preventive film disposed on thelateral surface of the trench in the direction of crossing the directionconnecting a source and a drain of the p-type field effect transistor inthe field region adjacent to the second active region surrounded withthe trench, and without disposing the oxidation preventive film on thelateral surface of the trench in the direction connecting a source and adrain of the p-type field effect transistor in the field region adjacentto the second active region surrounded with the trench; removing the padoxide film and the nitride film in the first and the second activeregions; and forming an n-type field effect transistor in the firstactive region, and forming a p-type field effect transistor in thesecond active region.
 11. A method of manufacturing a semiconductordevice according to claim 10, further comprising the steps of: formingan oxidation preventive film on a lateral surface of the trench of thefield region adjacent to the first active region and to a lateralsurface of the trench in the field region adjacent to the second activeregion; and removing the oxidation preventive film on the lateralsurface of the trench in the field region adjacent to the second activeregion.